1. Field of the Invention
The present invention relates to a method for implanting ions into a semiconductor substrate and, more particularly, to a method for implanting ions into a side wall of a protruded semiconductor layer on a semiconductor substrate.
2. Description of the Related Art
In a production process for a large-scale semiconductor integrated circuit employing a so-called planar technique, minute semiconductor elements are formed in a plane on a surface of a semiconductor substrate. For the formation of the semiconductor elements, diffusion layers each serving as an N-conductivity region or a P-conductivity region are generally formed in the semiconductor substrate by utilizing an ion implantation technique.
In the ion implantation technique, an impurity to be implanted is ionized, and the resulting ions are accelerated by an electric field and implanted into semiconductor crystals in the semiconductor substrate. The implanted ions collide against atoms and electrons in the semiconductor crystals and scatter in the semiconductor crystals, thereby losing energy to stop after traveling a predetermined distance in the semiconductor crystals. Where the ions are implanted along a line normal to the surface of the semiconductor substrate to selectively form a diffusion layer in a portion of the semiconductor substrate exposed through a mask opening, the implanted ions diffuse depthwise in the semiconductor substrate with a certain ion concentration distribution. The implanted ions also diffuse laterally in the semiconductor substrate with a certain ion concentration distribution. FIG. 9(a) is a sectional view of a P-type semiconductor substrate 10 which has an N-type diffusion layer 20 formed therein, for example, by implanting phosphorus ions into the semiconductor substrate 10 by applying a phosphorus ion beam 70 through an opening provided in a resist 50 formed on the substrate 10 by the ion implantation method. FIG. 9(b) is a characteristic diagram illustrating an impurity concentration distribution (the distribution of the concentration of the implanted phosphorus ions) in a sectional plane A–A′ in FIG. 9(a). As shown in FIG. 9(b), the impurity concentration distribution is such that the impurity concentration is the highest at the surface of the semiconductor substrate and decreases depthwise apart from the surface of the substrate. A region of the semiconductor substrate having a higher impurity concentration is the N-type diffusion region. In a semiconductor substrate region deeper than the N-type diffusion region, an intrinsic impurity of the semiconductor substrate is uniformly distributed.
In a so-called oblique ion implantation technique, ions are implanted into a semiconductor substrate at a certain angle θ with respect to a line normal to a surface of the semiconductor substrate for expanding a lateral impurity distribution or for preventing channeling. FIG. 10(a) is a sectional view of a P-type semiconductor substrate 10 which has an N-type diffusion layer 20 formed therein, for example, by implanting phosphorus ions into the semiconductor substrate 10 by applying a phosphorus ion beam 70 at an angle θ with respect to a line normal to a surface of the substrate 10 through an opening provided in a resist 50 formed on the substrate 10. FIG. 10(b) is a characteristic diagram illustrating an impurity concentration distribution (the distribution of the concentration of the implanted phosphorus ions) in a sectional plane B-B′ in FIG. 10(a). The depthwise impurity concentration distribution in the plane B–B′ is substantially the same as in FIG. 9(b). The oblique ion implantation technique makes it possible to implant the ions not only perpendicularly to the surface of the semiconductor substrate but also parallel to the surface of the semiconductor substrate. FIG. 11 is a sectional view of a P-type semiconductor substrate 10 which has an N-type diffusion layer 20 formed in a surface portion of the substrate and a side wall of a step of the substrate exposed through an opening provided in a resist 50 formed on the substrate 10. The formation of the diffusion layer 20 on the side wall of the step is achieved, for example, by implanting phosphorus ions into the semiconductor substrate 10 by applying a phosphorus ion beam 70 at an angle θ with respect to a line normal to the surface of the semiconductor substrate 10. The oblique ion implantation method is employed, for example, for forming an N-type MOS transistor of a gate overlap LDD structure to minimize an overlap on a source side for microminiaturization of a semiconductor device (see, for example, Japanese Unexamined Patent Publication No. 05-114608 (1993)). Further, the oblique ion implantation method is employed for introducing an impurity into a trench side wall for highly accurately forming a device isolation region in a self-aligning manner (see, for example, Japanese Unexamined Patent Publication No. 2000-183154).
However, it is difficult to implant ions into a portion of the semiconductor substrate perpendicular to the substrate surface by the aforesaid oblique ion implantation. This is because it is difficult to form a mask opening to expose only the portion of the substrate perpendicular to the substrate surface by a photolithography method employed in the so-called planar technique in which circuit elements such as transistors are formed in a plane on the semiconductor substrate.
In recent years, however, there is an increasing need for micro-processing and higher density integration of circuit elements. For example, nonvolatile memories typified by flash EEPROMs have found extensive application as higher-capacity and smaller-size information recording media for computers, communication devices, measurement instruments, automated control devices and personal daily life devices. Hence, there is an increasing demand for less expensive and higher-capacity nonvolatile memory cells. However, the size of such a memory cell is determined by a minimum processing dimension (feature size) which is defined by a resolution limit of the photolithography technique. In order to achieve higher density integration without relying on the improvement of the photolithography technique, a three-dimensional memory cell arrangement technique has been developed. In the three-dimensional memory cell arrangement technique, the number of integrated memory cells is increased by stacking the memory cells perpendicularly to the surface of the semiconductor substrate for the higher density integration.
In order to stack circuit elements such as transistors of the memory cells perpendicularly to the surface of the semiconductor substrate by utilizing the three-dimensional memory cell arrangement technique, there is a demand for an ion implantation technique which permits highly accurate control of ion implantation for implanting ions into a side wall of a semiconductor substrate, i.e., in a direction parallel to the surface of the semiconductor substrate.